library ieee;
use ieee.std_logic_1164.all;

entity writeback is
    port(
    RegWriteInW, MemToRegW:
        in std_logic;
    WriteRegInW:
        in std_logic_vector(4 downto 0);
    AluOutW, ReadDataW:
        in std_logic_vector(31 downto 0);

    RegWriteOutW:
        out std_logic;
    WriteRegOutW:
        out std_logic_vector(4 downto 0);
    ResultW:
        out std_logic_vector(31 downto 0)
    );
end writeback;

architecture behav of writeback is
    component mux2
        generic(n: integer);
        port(
        d0, d1: in std_logic_vector(n downto 0);
        s: in std_logic;
        y: out std_logic_vector(n downto 0)
        );
    end component;

begin
    WB_mux2: mux2
        generic map(31)
        port map(AluOutW, ReadDataW, MemToRegW, ResultW);

    RegWriteOutW <= RegWriteInW;
    WriteRegOutW <= WriteRegInW;
end behav;
